1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and, more particularly the present invention relates to a semiconductor integrated circuit device for use in fast and low power operation properties.
2. Description of the Background
As described in “Design Challengers of Technology Scaling” IEEE MICRO vol. 19, No. 4, pp 23-29, 1999 (“document”), the power consumption of microprocessors and other such chips is increasing year after year. In the year 2000, some chips appeared on the market with a power consumption exceeding 100 W.
As described in document 1, the power consumption caused by a leakage current also increases exponentially as the fabrication process produces smaller circuits. In particular, an increase in the subthreshold leakage current has been noted. In addition to the subthreshold leakage current, junction leakage currents such as the gate channeling current and the GIDL (Gate-Induced Drain Leakage) current increase as the fabrication process produces smaller circuits as described in “Identifying defects in deep-submicron CMOS ICs” IEEE Spectrum pp-66-71, September, 1996 (“document 2”).
As described in document 1, power consumption Pac caused by charging/discharging of a load among the power consumption types in the active state of the above chip is proportional to the result of (operation frequency f).times.(load capacity C).times.(supply voltage V).times.(supply voltage V). Typically, therefore, a low voltage has been used as a supply voltage (hereafter, “conventional example 1”).
In order to reduce power consumption Psi caused by the sub-threshold leakage current in the standby state of the subject circuit, “Subthreshold-Current Reduction Circuits for Multi-Gigabit PRAMs”, Symposium on VLSI Circuits Digest of Technical Papers, pp 45-46, May 1993 (“document 3”) proposes a power switch method. According to the method, a power switch is disposed between a power line and a circuit, and the power switch is turned off when the circuit stands by (hereafter, “conventional example 2”).
In addition, “50% Active-Power Saving without Speed Degradation using Standby Power Reduction (SPR) Circuit”, ISSCC Digest of Technical Papers, pp 318-319, 1995″ (“document 4”) proposes a substrate bias control method. According to the method, the voltage of a substrate terminal of a MOS transistor of the subject circuit is switched between active and standby states and the threshold voltage of the MOS transistor is switched between active and standby states, thereby reducing the subthreshold leakage current in the standby state (hereafter, “conventional example 3”).
Furthermore, “Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS (DOT-MTCMOS)”, Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, pp. 264-265, 1999 (“document 5”) describes a method for reducing power consumption pg l caused by the gate tunneling current in the standby state. According to the method, a thick oxide PMOS transistor is disposed between a circuit configured by a thin oxide MOS transistor and a power line, and the power switch is thereafter turned off while the circuit stands by, thereby reducing the power consumption caused by the gate tunneling current in the standby state (hereafter, “conventional example 4”).
Alternatively, a method for managing chip level power consumption is disclosed in the official gazette of JP-A-152945/1996. According to this method, each function block requests a power management, apparatus for a necessary power according to the load state, and the power management apparatus calculates the total power consumption requested from the function blocks. When the total requested power is within the maximum supply power available, the power management apparatus allows the requested power to be sent to the functional blocks. When the total power exceeds the maximum supply power, the power management apparatus controls the clock frequency and the supply voltage of each function block so that the total requested power does not exceed the maximum supply power.
However, this disclosed method gives no consideration to the current in the standby state, which is increasing as described above. Because the power management apparatus cannot disable the operation of each function block, the integration of a circuit according to any of the methods in the conventional examples has been limited. In addition, where the power management apparatus controls the clock frequency and the supply voltage of each function block, the power consumption required for controlling the apparatus itself is not taken into account. Thus, the power of a chip to be controlled by the conventional methods has been limited.
Along with an increase in the number of functions required for microprocessors or other such chips, the number of MOS transistors integrated on these chips, as well as their operational frequency, also is increasing. Consequently, power consumption Pac caused by the charging/discharging of the circuit load also increases. The method of conventional example 1, when reducing this power consumption Pac, cannot completely address the incremental trend of the power consumption Pac because to keep or improve the operational speed of a chip in the state of lowered supply voltage, where the Pac generally can be reduced, requires lower-setting of a threshold voltage for each MOS transistor of the chip or reducing the gate oxide thickness of the MOS transistor, causing both Psl and Pgl to be increased exponentially. In spite of these problems, the method of conventional example 1 has typically been considered the most effective for reducing the Pac value. The method has thus been used widely as described in document 1.
Both Psl and Pgl have also increased year after year as described in documents 1 and 2. Although the methods of conventional examples 2 through 4 are proposed to suppress an increase of Psl and Pgl, those methods can reduce neither the Psl nor the Pgl while the chip is active. These methods can only reduce Psl and Pgl while the chip stands by. The methods in conventional examples 2 through 4 are effective only when the power consumption values (Pgl and Pgl) caused by the subthreshold leakage current and a gate channeling current can be ignored with respect to the Pac value, since reduction of the Pgl and the Pgl is only required in the standby state in which the Pac becomes almost zero. Where both Pgl and Pgl are too large to be ignored with respect to the Pac value, however, the Pgl and the Pgl may significantly affect the power consumption of the chip in the active state. None of the methods in the conventional examples 2 through 4 is therefore effective in reducing the power consumption.